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<h3><b><a name="top">Memory Device</a></b></h3>

<p>Use this window to view information for a particular memory device.</p>

<table border="0" cellpadding="4" cellspacing="3" width="80%">
  <tr>
    <td class="data-area-canvas-odd" vAlign="top" width="30%" align="left"><strong>Status</strong></td>
    <td class="data-area-canvas-odd" vAlign="top" width="70%" align="left">Normal, prefailure,
    or failure performance of the connector or slot for a memory module.</td>
  </tr>
  <tr>
    <td class="data-area-canvas" vAlign="top" width="30%" align="left"><strong>Device Name</strong></td>
    <td class="data-area-canvas" vAlign="top" width="70%" align="left">The alphanumeric text
    that uniquely identifies each memory slot, whether occupied or unoccupied.</td>
  </tr>
  <tr>
    <td class="data-area-canvas" vAlign="top" width="30%" align="left"><strong>Size</strong></td>
    <td class="data-area-canvas" vAlign="top" width="70%" align="left">Capacity of the memory
    slot expressed in MB or GB.</td>
  </tr>
  <tr>
    <td class="data-area-canvas" vAlign="top" width="30%" align="left"><strong>Type</strong></td>
    <td class="data-area-canvas" vAlign="top" width="70%" align="left">Synchronous dynamic
    random access memory (SDRAM) chip sets operate fast enough to synchronize with the
      CPU clock, eliminating wait states. The SDRAM chip set has two cell
    blocks, allowing more efficient data access. In dynamic random access memory (DRAM) each bit
    of storage is built from a single transistor and capacitor, allowing more memory bits to
    fit in the same chip area. However, DRAM has to be refreshed because the charge on the
    capacitor, which represents the stored bit value, decays with time. During a refresh, the
    memory module must read every bit and write it back at full strength.&nbsp;</td>
  </tr>
  <tr>
    <td class="data-area-canvas" vAlign="top" width="30%" align="left"><strong>Speed</strong></td>
    <td class="data-area-canvas" vAlign="top" width="70%" align="left">The rate, in
    nanoseconds, at which the memory module can read the second and all contiguous characters
    in a data word. The standard rate for SDRAM is 10ns.</td>
  </tr>
  <tr>
    <td class="data-area-canvas" vAlign="top" width="30%" align="left"><strong>Failures</strong></td>
    <td class="data-area-canvas" vAlign="top" width="70%" align="left">If the value is other
    than None, one or more of the following strings is displayed: <ul>
      <li><span class="screen">Single bit warning error rate exceeded</span></li>
      <li><span class="screen">Single bit failure error rate exceeded</span></li>
      <li><span class="screen">Multi bit error encountered</span></li>
      <li><span class="screen">Single bit error login disabled</span></li>
      <li><span class="screen">DIMM disabled by way of spare memory activation</span></li>
    </ul>
    </td>
  </tr>
</table>

<p>[<a href="#top">Back to Top</a>]</p>

<h4>Other Window Controls&nbsp;</h4>

<table border="0" cellpadding="4" cellspacing="3" width="80%">
  <tr>
    <td width="30%" valign="top"><b>Go Back to Memory Page</b></td>
    <td width="70%" valign="top">Returns to the previous window.</td>
  </tr>
</table>

<p>[<a href="#top">Back to Top</a>]</p>

<p>&nbsp;</p>
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