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<h3><font color="#000080"><b>Capabilities and Cache Information</b></font></h3>
<p></p>Use this window to view a subset of key functions/properties that each processor
supports as well as cache information for and each cache present on that
processor.
<br>
<table width="80%" border="0" id="table6">
<tbody>
<tr>
<td vAlign="top" align="left" width="21"><img src="note.gif" border="0" width="17"
height="17"></td>
<td ><span class="notes"><b>NOTE</b>:</span> The fields
listed on this page cover possible configurations. Some fields may not be
present on your system.</td>
</tr>
</tbody>
</table>
<h4><b>Capable</b></h4>
<p>If the processor is capable of a particular function/property, this field
displays <b>True</b>, otherwise <b>False</b>. </p>
<h4><b>Enabled</b></h4>
<p>If a particular function/property of a processor is enabled, this field
displays <b>True</b>, otherwise <b>False.</b> If a function cannot be
enabled or disabled by user, <b>Not Applicable</b> is displayed. </p>
<h3><font color="#000080"><b>Capabilities Information for Processor</b></font> <n>
</h3>
<h4><b>Intel®</b></h4>
<table border="0" cellpadding="4" cellspacing="3" width="80%" id="table1">
<tr>
<td width="30%" valign="top" align="left"><strong>64-bit Support</strong></td>
<td width="70%" valign="top" align="left">Supports 64-bit. </td>
</tr>
<tr>
<td width="30%" valign="top" align="left">
<a id="Capabilities" name="Capabilities"><strong>Hyperthreading (HT)</strong></a></td>
<td width="70%" valign="top" align="left">Intel's implementation of the simultaneous multithreading
technology. </td>
</tr>
<tr>
<td width="30%" valign="top" align="left">
<a name="Capabilities0" id="Capabilities"><strong>Virtualization
Technology (VT)</strong></a></td>
<td width="70%" valign="top" align="left">
Intel's virtualization extension to the 64-bit x86 architecture. </td>
</tr>
<tr>
<td width="30%" valign="top" align="left">
<a name="Capabilities1" id="Capabilities"><strong>Demand Based Switching (DBS)</strong></a></td>
<td width="70%" valign="top" align="left">A power-management technology
developed by Intel in which the applied voltage and clock speed for a
microprocessor are kept to the minimum necessary to allow optimum
performance of required operations.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left">
<a name="Capabilities3" id="Capabilities1"><strong>Execute Disable (XD)</strong></a></td>
<td width="70%" valign="top" align="left">Allows properly-written
applications to mark off memory space as executable, so that code trying to
access space above and beyond that will not be <b>executed.</b></td>
</tr>
</table>
<h3><font color="#000080"><b><a name="top">Cache Information for Processor <i><n></i></a></b></font></h3>
<p>Use this window to view cache information for each cache present on the microprocessor.
</p>
<h4><b>Cache</b> </h4>
<p>Cache is small high-speed memory that contains the most recently accessed pieces of
main memory. The cache keeps a copy of data or instructions from main memory for
quicker retrieval. Cache decreases the amount of time it takes to move data from main
memory to the processor and back again. The processor cache is faster than the system's
main RAM. </p>
<h5>Cache Information for a Particular Processor on Connector <i>n</i></h5>
<table border="0" cellpadding="4" width="80%">
<tr>
<td valign="top"><img src="note.gif" alt="note.gif" width="17" height="17"></td>
<td><span class="notes">NOTE:</span> Some cache devices are internal to the processors on
which they reside. When the cache is internal to a processor, the following fields and
their values do not appear in the <b>Cache Information for Processor on Connector</b><i> <b>n
</b></i>window: <ul>
<li>Speed</li>
<li>Cache Device Supported Type</li>
<li>Cache Device Current Type</li>
<li>External Socket Name</li>
</ul>
</td>
</tr>
</table>
<p>The following fields are defined for a cache device on a particular processor. Some
fields do not appear if the cache is internal to the processor.</p>
<table width="80%" border="0">
<tbody>
<tr>
<td vAlign="top" align="left" width="21"><img src="note.gif" border="0" width="17"
height="17"></td>
<td><span class="notes"><b>NOTE</b>:</span> This help page may include
information about cache features that are not supported by your system. Server
Administrator only displays the cache features that are supported on your system.</td>
</tr>
</tbody>
</table>
<p> </p>
<table border="0" cellpadding="4" cellspacing="3" width="80%">
<tr>
<td width="30%" valign="top" align="left"><strong>Status</strong></td>
<td width="70%" valign="top" align="left">Indicates whether the cache on the processor is
enabled or disabled.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Level</strong></td>
<td width="70%" valign="top" align="left">Displays the cache level. Primary level cache
(<i>L1</i>) is a very fast memory bank located near the processor execution units. Secondary
level cache (<i>L2</i>) is a larger staging area that feeds the primary cache. Tertiary level
cache (<i>L3</i>), if available, is an additional, larger memory bank which feeds data to the
secondary cache. All of these cache levels are located in the processor. </td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Speed</strong></td>
<td width="70%" valign="top" align="left">Indicates the rate that the cache can forward
data from main memory to the processor.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Max Size</strong></td>
<td width="70%" valign="top" align="left">Displays the maximum memory that the cache can
occupy in KB.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Installed Size</strong></td>
<td width="70%" valign="top" align="left">Displays the actual size of the cache.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Type</strong></td>
<td width="70%" valign="top" align="left">Indicates whether the cache type is
<i> Data</i> or <i>Unified</i>.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Location</strong></td>
<td width="70%" valign="top" align="left">Indicates whether the cache is located on the
processor or on a chip set outside the processor.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Write Policy</strong></td>
<td width="70%" valign="top" align="left">Describes how the cache deals with a write
cycle. <p>In a <em>Write-Back</em> policy, the cache acts like a buffer. When the
processor starts a write cycle, the cache receives the data and stops the cycle. The cache
then writes the data back to main memory when the system bus is available. </p>
<p>In a <em>Write-Through</em> policy, the processor writes through the cache to main
memory. The write cycle does not complete until the data is stored into main memory. </p>
<p>If the write policy specifies <em>Varies with Address</em>, then the policy is either
write-back or write-through, according to the memory address.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Associativity</strong></td>
<td width="70%" valign="top" align="left"><em>Fully Associative</em> cache allows any line
in main memory to be stored at any location in the cache. <p><em>8-Way Set-Associative</em><b>
</b>cache directly maps eight specific lines of memory to the same eight lines of
cache. </p>
<p><em>4-Way Set-Associative</em><b> </b>cache directly maps four specific lines of memory
to the same four lines of cache. </p>
<p><em>3-Way Set-Associative</em> cache directly maps three specific lines of memory to
the same three lines of cache. </p>
<p><em>2-Way Set-Associative</em> cache directly maps two specific lines of memory to the
same two lines of cache. </p>
<p><em>1-Way Set-Associative</em> cache directly maps a specific line of memory in the
same line of cache. For example, Line 0 of any page in memory must be stored in Line 0 of
cache memory.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Cache Device Supported Type</strong></td>
<td width="70%" valign="top" align="left">Indicates the type of static random access
memory (SRAM) that the device can support.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Cache Device Current Type</strong></td>
<td width="70%" valign="top" align="left">Indicates the type of the currently installed
SRAM that the cache is supporting.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>External Socket Name</strong></td>
<td width="70%" valign="top" align="left">Silk-screen name printed on the system board
next to the socket.</td>
</tr>
<tr>
<td width="30%" valign="top" align="left"><strong>Error Correction Type</strong></td>
<td width="70%" valign="top" align="left">Identifies the type of error checking and
correction (ECC) that this memory can perform. For example, single-bit ECC or multibit
ECC.</td>
</tr>
</table>
<p>[<a href="#top">Back to Top</a>]</p>
<h4>Other Window Controls</h4>
<table cellSpacing="3" cellPadding="4" width="80%" border="0" id="table2">
<tr>
<td vAlign="top" align="left" width="30%"><b>Print</b></td>
<td vAlign="top" align="left" width="70%"><font color="#000000">Prints a
copy of the open window to your default printer.</font></td>
</tr>
</table>
<table cellSpacing="3" cellPadding="4" width="80%" border="0" id="table3">
<tr>
<td vAlign="top" width="30%"><b>Export</b></td>
<td vAlign="top" width="70%">Saves a text file containing the contents
of this window (the values of each data field separated by a
customizable delimiter) to a destination you specify.</td>
</tr>
</table>
<table cellSpacing="3" cellPadding="4" width="80%" border="0" id="table4">
<tr>
<td vAlign="top" align="left" width="30%"><b>Email</b></td>
<td vAlign="top" align="left" width="70%">E-mails the contents of this
window to your designated recipient. See the <em>Server Administrator
User's Guide</em> for instructions about configuring your Simple Mail
Transfer Protocol (SMTP) server.</td>
</tr>
<tr>
<td vAlign="top" align="left" width="30%"><b>Refresh</b></td>
<td vAlign="top" align="left" width="70%">Updates the screen with latest
information. </td>
</tr>
</table>
<p>[<a href="#top">Back to Top</a>]</p>
<p> </p>
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